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| ltc2495 2495fd features a pplications description 16-bit 8-/16-channel d s adc with pga, easy drive and i 2 c interface the ltc ? 2495 is a 16-channel (eight differential), 16-bit, no latency ds tm adc with easy drive technology and a 2-wire, i 2 c interface. the patented sampling scheme elimi - nates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. this allows large external source impedances and rail-to-rail input signals to be directly digitized while maintaining exceptional dc accuracy. the ltc2495 includes programmable gain, a high accuracy temperature sensor, and an integrated oscillator. this device can be confgured to measure an external signal (from com - binations of 16 analog input channels operating in single- ended or differential modes) or its internal temperature sensor. the integrated temperature sensor offers 1/2c resolution and 2c absolute accuracy. the ltc2495 can be confgured to provide a programmable gain from 1 to 256 in 8 steps. the ltc2495 allows a wide common mode input range (0v to v cc ), independent of the reference voltage. any combination of single-ended or differential inputs can be selected and the frst conversion, after a new channel is selected, is valid. access to the multiplexer output en - ables optional external amplifers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift. data acquisition system with temperature compensation n up to eight differential or 16 single-ended inputs n easy drive tm technology enables rail-to-rail inputs with zero differential input current n directly digitizes high impedance sensors with full accuracy n 2-wire i 2 c interface with 27 addresses plus one global address for synchronization n 600nv rms noise n programmable gain from 1 to 256 n integrated high accuracy temperature sensor n gnd to v cc input/reference common mode range n programmable 50hz, 60hz, or simultaneous 50hz/60hz rejection mode n 2ppm inl, no missing codes n 1ppm offset and 15ppm full-scale error n 2x speed/reduced power mode (15hz using internal oscillator and 80a at 7.5hz output) n no latency: digital filter settles in a single cycle, even after a new channel is selected n single supply 2.7v to 5.5v operation (0.8mw) n internal oscillator n tiny 5mm 7mm qfn package n direct sensor digitizer n direct temperature measurement n instrumentation n industrial process control built-in high performance temperature sensor sc l sda f o re f + v cc muxout/ adcin muxout/ adcin 2.7v to 5.5v 10f 1.7k com re f ? 16-bit $ 3 adc with easy drive 16-channel mux temperature sensor in + in ? 2495 ta01 2-wire i 2 c interface ch0 ch1 ? ? ? ? ? ? ch7 ch8 ch15 0.1f osc temperature (c) ?55 ?30 ?5 absolute error (c) 5 4 3 2 1 ?4 ?3 ?2 ?1 0 120 95 70 45 20 2495 ta02 ?5 t ypical a pplication l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no latency ds and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2495 2495fd p in c on f iguration a bsolute maxi m u m r atings supply voltage (v cc ) ................................... C0.3v to 6v analog input voltage (ch0-ch15, com) .................... C0.3v to (v cc + 0.3v) ref + , ref C ............................... C0.3v to (v cc + 0.3v) adcinn, adcinp, muxoutp, muxoutn ................................ C0.3v to (v cc + 0.3v) digital input voltage ...................... C0.3v to (v cc + 0.3v) digital output voltage ................... C0.3v to (v cc + 0.3v) operating temperature range ltc2495c ................................................ 0c to 70c ltc2495i ............................................. C40c to 85c storage temperature range .................. C65c to 150c (notes 1, 2) 13 14 15 16 top view 39 uhf package 38-lead (5mm s 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd scl sda gnd nc gnd com ch0 ch1 ch2 ch3 ch4 gnd ref ? ref + v cc muxoutn adcinn adcinp muxoutp ch15 ch14 ch13 ch12 ca2 ca1 ca0 f o gnd gnd gnd ch5 ch6 ch7 ch8 ch9 ch10 ch11 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin #39) is gnd, must be soldered to pcb e lectrical c haracteristics ( n or m al s pee d ) the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , Cfs v in +fs (note 5) 16 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l l 2 1 20 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 13) l 0.5 5 v offset error drift 2.5v v ref v cc , gnd in + = in C v cc 10 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref l 32 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref l 32 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref 0.1 ppm of v ref /c or d er in f or m ation lead free finish tape and reel part marking* package description temperature range ltc2495cuhf#pbf ltc2495cuhf#trpbf 2495 38-lead (5mm 7mm) plastic qfn 0c to 70c ltc2495iuhf#pbf ltc2495iuhf#trpbf 2495 38-lead (5mm 7mm) plastic qfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ ltc2495 2495fd e lectrical c haracteristics (2x s pee d ) the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , Cfs v in +fs (note 5) 16 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l 2 1 20 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 13) l 0.2 2 mv offset error drift 2.5v v ref v cc , gnd in + = in C v cc 100 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref l 32 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref l 32 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref 0.1 ppm of v ref /c output noise 5v v cc 5.5v, v ref = 5v, gnd in + = in C v cc 0.85 v rms programmable gain l 1 128 c onverter c haracteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in + = in C v cc (note 5) l 140 db input common mode rejection 50hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 7) l 140 db input common mode rejection 60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 8) l 140 db input normal mode rejection 50hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 7) l 110 120 db input normal mode rejection 60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 8) l 110 120 db input normal mode rejection 50hz/60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 9) l 87 db reference common mode rejection dc 2.5v v ref v cc , gnd in + = in C v cc (note 5) l 120 140 db power supply rejection dc v ref = 2.5v, in + = in C = gnd 120 db power supply rejection, 50hz 2%, 60hz 2% v ref = 2.5v, in + = in C = gnd (notes 7, 8, 9) 120 db parameter conditions min typ max units total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 15 15 15 ppm of v ref ppm of v ref ppm of v ref output noise 2.7v < v cc < 5.5v, 2.5v v ref v cc , gnd in + = in C v cc (note 12) 0.6 v rms internal ptat signal t a = 27c (note 13) 27.8 28.0 28.2 mv internal ptat temperature coeffcient 93.5 v/c programmable gain l 1 256 e lectrical c haracteristics ( n or m al s pee d ) the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (notes 3, 4) a nalog i nput an d r e f erence the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage (in + corresponds to the selected positive input channel) gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage (in C corresponds to the selected negative input channel) gnd C 0.3v v cc + 0.3v v ltc2495 2495fd i 2 c i nputs a n d digital o utputs the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) a nalog i nput an d r e f erence the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage l 0.7v cc v v il low level input voltage l 0.3v cc v v iha low level input voltage for address pins ca0, ca1, ca2 and pin f o l 0.05v cc v v ila high level input voltage for address pins ca0, ca1, ca2 l 0.95v cc v r inh resistance from ca0, ca1, ca2 to v cc to set chip address bit to 1 l 10 k w r inl resistance from ca0, ca1, ca2 to gnd to set chip address bit to 0 l 10 k w r inf resistance from ca0, ca1, ca2 to gnd or v cc to set chip address bit to float l 2 m w i i digital input current (f o ) l C10 10 a v hys hysteresis of schmitt trigger inputs (note 5) l 0.05v cc v v ol low level output voltage (sda) i = 3ma l 0.4 v t of output fall time v ih(min) to v il(max) bus load c b 10pf to 400pf (note 14) l 20 + 0.1c b 250 ns i in input leakage (sda/scl) 0.1v cc v in 0.9 ? v cc l 1 a c cax external capacitative load on chip address pins (ca0, ca1, ca2) for valid float l 10 pf p ower r equire m ents the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion current (note 11) temperature measurement (note 11) sleep mode (note 11) l l l 160 200 1 275 300 2 a a a v in input differential voltage range (in + C in C ) l Cfs +fs v fs full-scale of the differential input (in + C in C ) l 0.5v ref /gain v lsb least signifcant bit of the output code l fs/2 16 ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd ref + C 0.1v v v ref reference voltage range (ref + C ref C ) l 0.1 v cc v cs(in + ) in + sampling capacitance 11 pf cs(in C ) in C sampling capacitance 11 pf cs(v ref ) v ref sampling capacitance 11 pf i dc_leak(in + ) in + dc leakage current sleep mode, in + = gnd l C10 1 10 na i dc_leak(in C ) in C dc leakage current sleep mode, in C = gnd l C10 1 10 na i dc_leak(ref + ) ref + dc leakage current sleep mode, ref + = v cc l C100 1 100 na i dc_leak(ref C ) ref C dc leakage current sleep mode, ref C = gnd l C100 1 100 na t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db ltc2495 2495fd symbol parameter conditions min typ max units f eosc external oscillator frequency range (note 16) l 10 4000 khz t heo external oscillator high period l 0.125 100 s t leo external oscillator low period l 0.125 100 s t conv_1 conversion time for 1x speed mode 50hz mode 60hz mode simultaneous 50hz/60hz mode external oscillator (note 10) l l l 157.2 131 144.1 160.3 133.6 146.9 41036/f eosc (in khz) 163.5 136.3 149.9 ms ms ms ms t conv_2 conversion time for 2x speed mode 50hz mode 60hz mode simultaneous 50hz/60hz mode external oscillator (note 10) l l l 78.7 65.6 72.2 80.3 66.9 73.6 20556/f eosc (in khz) 81.9 68.2 75.1 ms ms ms ms digital i nputs a n d digital o utputs the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sda) hold time (repeated) start condition l 0.6 s t low low period of the scl pin l 1.3 s t high high period of the scl pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time for sda signals (note 14) l 20 + 0.1c b 300 ns t f fall time for sda signals (note 14) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a second start condition l 1.3 s i 2 c ti m ing characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3, 15) no te 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: unless otherwise specifed: v cc = 2.7v to 5.5v v refcm = v ref /2, f s = 0.5v ref /gain v in = in + C in C , v in(cm) = (in + C in C )/2, where in + and in C are the selected input channels. note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless otherwise specifed. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: 50hz mode (internal oscillator) or f eosc = 256khz 2% (external oscillator). note 8: 60hz mode (internal oscillator) or f eosc = 307.2khz 2% (external oscillator). note 9: simultaneous 50hz/60hz mode (internal oscillator) or f eosc = 280khz 2% (external oscillator). note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses its internal oscillator. note 12: the output noise includes the contribution of the internal calibration operations. note 13: guaranteed by design and test correlation. note 14: c b = capacitance of one bus line in pf (10pf c b 400pf). note 15: all values refer to v ih(min) and v il(max) levels. note 16: refer to applications information section for performance vs data rate graphs. ltc2495 2495fd t ypical p er f or m ance c haracteristics integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) noise histogram (6.8sps) noise histogram (7.5sps) input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?1.5 ?0.5 0.5 1.5 2495 g01 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c ?45c 25c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2495 g02 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd ?45c, 25c, 85c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2495 g03 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd ?45c, 25c, 85c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?1.5 ?0.5 0.5 1.5 2495 g04 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c 25c ?45c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?0.75 ?0.25 0.25 0.75 2495 g05 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c ?45c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?0.75 ?0.25 0.25 0.75 2495 g06 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c ?45c output reading (v) ?3 number of readings (%) 8 10 12 0.6 2495 g07 6 4 ?1.8 ?0.6 ?2.4 1.2 ?1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v t a = 25c gain = 256 rms = 0.60v average = ?0.69v output reading (v) ?3 number of readings (%) 8 10 12 0.6 2495 g08 6 4 ?1.8 ?0.6 ?2.4 1.2 ?1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v t a = 25c gain = 256 rms = 0.59v average = ?0.19v ltc2495 2495fd t ypical p er f or m ance c haracteristics long-term adc readings rms noise vs input differential voltage rms noise vs v in(cm) rms noise vs temperature (t a ) rms noise vs v cc rms noise vs v ref offset error vs v in(cm) offset error vs temperature time (hours) 0 ?5 adc reading (v) ?3 ?1 1 10 20 30 40 2495 g09 50 3 5 ?4 ?2 0 2 4 60 v cc = 5v v ref = 5v v in = 0v v in(cm) = 2.5v t a = 25c rms noise = 0.60v gain = 256 input differential voltage (v) 0.4 rms noise (v) 0.6 0.8 1.0 0.5 0.7 0.9 ?1.5 ?0.5 0.5 1.5 2495 g10 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c f o = gnd v in(cm) (v) ?1 rms noise (v) 0.8 0.9 1.0 2 4 2495 g11 0.7 0.6 0 1 3 5 6 0.5 0.4 v cc = 5v v ref = 5v v in = 0v t a = 25c f o = gnd gain = 256 temperature (c) ?45 0.4 rms noise (v) 0.5 0.6 0.7 0.8 1.0 ?30 ?15 15 0 30 45 60 2495 g12 75 90 0.9 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd gain = 256 v cc (v) 2.7 rms noise (v) 0.8 0.9 1.0 3.9 4.7 2495 g13 0.7 0.6 3.1 3.5 4.3 5.1 5.5 0.5 0.4 v ref = 2.5v v in = 0v v in(cm) = gnd t a = 25c f o = gnd gain = 256 v ref (v) 0 0.4 rms noise (v) 0.5 0.6 0.7 0.8 0.9 1.0 1 2 3 4 2495 g14 5 v cc = 5v v in = 0v v in(cm) = gnd t a = 25c f o = gnd gain = 256 v in(cm) (v) ?1 offset error (ppm of v ref ) 0.1 0.2 0.3 2 4 2495 g15 0 ?0.1 0 1 3 5 6 ?0.2 ?0.3 v cc = 5v v ref = 5v v in = 0v t a = 25c f o = gnd temperature (c) ?45 ?0.3 offset error (ppm of v ref ) ?0.2 0 0.1 0.2 ?15 15 30 90 2495 g16 ?0.1 ?30 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd ltc2495 2495fd t ypical p er f or m ance c haracteristics on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature temperature (c) ?45 ?30 300 frequency (khz) 304 310 ?15 30 45 2495 g19 302 308 306 15 0 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.5 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2495 g20 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c frequency at v cc (hz) 1 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 1k 100k 2495 g21 10 100 10k 1m rejection (db) v cc = 4.1v dc v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25 o c frequency at v cc (hz) 0 ?140 rejection (db) ?120 ?80 ?60 ?40 0 20 100 140 2495 g22 ?100 ?20 80 180 220 200 40 60 120 160 v cc = 4.1v dc p 1.4v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25 o c frequency at v cc (hz) 30600 ?60 ?40 0 30750 2495 g23 ?80 ?100 30650 30700 30800 ?120 ?140 ?20 rejection (db) v cc = 4.1v dc p 0.7v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25 o c temperature (c) ?45 100 conversion current (a) 120 160 180 200 ?15 15 30 90 2495 g24 140 ?30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd offset error vs v cc offset error vs v ref v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2495 g17 0 ?0.1 3.1 3.5 4.3 5.1 5.5 ?0.2 ?0.3 ref + = 2.5v ref ? = gnd v in = 0v v in(cm) = gnd t a = 25c f o = gnd v ref (v) 0 ?0.3 offset error (ppm of v ref ) ?0.2 ?0.1 0 0.1 0.2 0.3 1 2 3 4 2495 g18 5 v cc = 5v ref ? = gnd v in = 0v v in(cm) = gnd t a = 25c f o = gnd ltc2495 2495fd t ypical p er f or m ance c haracteristics sleep mode current vs temperature conversion current vs output data rate integral nonlinearity (2x speed mode; v cc = 5v, v ref = 5v) integral nonlinearity (2x speed mode; v cc = 5v, v ref = 2.5v) integral nonlinearity (2x speed mode; v cc = 2.7v, v ref = 2.5v) noise histogram (2x speed mode) rms noise vs v ref (2x speed mode) offset error vs v in(cm) (2x speed mode) temperature (c) ?45 0 sleep mode current (a) 0.2 0.6 0.8 1.0 2.0 1.4 ?15 15 30 90 2495 g25 0.4 1.6 1.8 1.2 ?30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd output data rate (readings/sec) 0 supply current (a) 500 450 400 350 300 250 200 150 100 80 2495 g26 20 40 60 100 70 10 30 50 90 v cc = 5v v cc = 3v v ref = v cc in + = gnd in ? = gnd f o = ext osc t a = 25c input voltage (v) ?3 inl (v) ?1 1 3 ?2 0 2 ?1.5 ?0.5 0.5 1.5 2495 g27 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 25c, 85c ?45c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2495 g28 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c ?45c, 25c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2495 g29 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c ?45c, 25c output reading (v) 179 number of readings (%) 8 10 12 186.2 2495 g30 6 4 181.4 183.8 188.6 2 0 16 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v t a = 25c gain = 128 rms = 0.85v average = 0.184v v ref (v) 0 rms noise (v) 0.6 0.8 1.0 4 2495 g31 0.4 0.2 0 1 2 3 5 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c gain = 128 v in(cm) (v) ?1 180 offset error (v) 182 186 188 190 200 194 1 3 4 2495 g32 184 196 198 192 0 2 5 6 v cc = 5v v ref = 5v v in = 0v f o = gnd t a = 25c ltc2495 0 2495fd t ypical p er f or m ance c haracteristics psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) frequency at v cc (hz) 1 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 1k 100k 2495 g36 10 100 10k 1m rejection (db) v cc = 4.1v dc ref + = 2.5v ref ? = gnd in + = gnd in ? = gndf f o = gnd t a = 25c frequency at v cc (hz) 0 ?140 rrejection (db) ?120 ?80 ?60 ?40 0 20 100 140 2495 g37 ?100 ?20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 ?60 ?40 0 30750 2495 g38 ?80 ?100 30650 30700 30800 ?120 ?140 ?20 rejection (db) v cc = 4.1v dc 0.7v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c offset error vs v cc (2x speed mode) offset error vs v ref (2x speed mode) v cc (v) 2 2.5 0 offset error (v) 100 250 3 4 4.5 2495 g34 50 200 150 3.5 5 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c v ref (v) 0 offset error (v) 190 200 210 3 5 2495 g35 180 170 160 1 2 4 220 230 240 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c offset error vs temperature (2x speed mode) temperature (c) ?45 offset error (v) 200 210 220 75 2495 g33 190 180 160 ?15 15 45 ?30 90 0 30 60 170 240 230 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd ltc2495 2495fd gnd (pins 1, 4, 6, 31, 32, 33, 34): ground. multiple ground pins internally connected for optimum ground cur - rent fow and v cc decoupling. connect each one of these pins to a common ground plane through a low impedance connection. all seven pins must be connected to ground for proper operation. scl (pin 2): serial clock pin of the i 2 c interface. the ltc2495 can only act as a slave and the scl pin only ac - cepts an external serial clock. data is shifted into the sda pin on the rising edges of the scl clock and output through the sda pin on the falling edges of the scl clock. sda (pin 3): bidirectional serial data line of the i 2 c inter - face. in the transmitter mode (read), the conversion result is output through the sda pin, while in the receiver mode (write), the device channel select and confguration bits are input through the sda pin. the pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to v cc ) during the data output mode. nc (pin 5): no connect. this pin can be left foating or tied to gnd. com (pin 7): the common negative input (in C ) for all single-ended multiplexer confgurations. the voltage on ch0-ch15 and com pins can have any value between gnd C 0.3v to v cc + 0.3v. within these limits, the two selected inputs (in + and in C ) provide a bipolar input range v in = (in + C in C ) from C0.5 ? v ref /gain to 0.5 ? v ref /gain. outside this input range, the converter produces unique over-range and under-range output codes. ch0 to ch15 (pin 8-pin 23): analog inputs. may be pro - grammed for single-ended or differential mode. muxoutp (pin 24): positive multiplexer output. connect to the input of external buffer/amplifer or short directly to adcinp. adcinp (pin 25): positive adc input. connect to the output of a buffer/amplifer driven by muxoutp or short directly to muxoutp. adcinn (pin 26): negative adc input. connect to the output of a buffer/amplifer driven by muxoutn or short directly to muxoutn. muxoutn (pin 27): negative multiplexer output. con - nect to the input of an external buffer/amplifer or short directly to adcinn. v cc (pin 28): positive supply voltage. bypass to gnd with a 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor as close to the part as possible. ref + , ref C (pin 29, pin 30): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , remains more positive than the negative reference input, ref C , by at least 0.1v. the differential voltage (v ref = ref + C ref C ) sets the full-scale range (C0.5 ? v ref /gain to 0.5 ? v ref /gain) for all input channels. when performing an on-clip temperature measurement, the minimum value of ref = 2v. f o (pin 35): frequency control pin. digital input that controls the internal conversion clock rate. when f o is connected to gnd, the converter uses its internal oscil - lator running at 307.2khz. the conversion clock may also be overridden by driving the f o pin with an external clock in order to change the output rate and the digital flter rejection null. ca0, ca1, ca2 (pins 36, 37, 38): chip address control pins. these pins are confgured as a three-state (low, high, floating) address control bits for the device i 2 c address. exposed pad (pin 39): ground. this pin is ground and must be soldered to the pcb ground plane. for prototyping purposes, this pin may remain foating. p in functions ltc2495 2495fd f unctional b lock diagra m autocalibration and control differential 3rd order $ 3 modulator decimating fir address internal oscillator i 2 c 2-wire interface gnd v cc ch0 ch1 ? ? ? ch15 com mux sda ref + ref ? adcinn muxoutn adcinp muxoutp scl f o (int/ext) 2495 bd + ? temp sensor ltc2495 2495fd converter operation converter operation cycle the ltc2495 is a multichannel, low power, delta-sigma, analog-to-digital converter with a 2-wire, i 2 c interface. its operation is made up of four states (see figure 1). the converter operating cycle begins with the conver - sion, followed by the sleep state, and ends with the data input/output cycle. initially, at power-up, the ltc2495 performs a conversion. once the conversion is complete, the device enters the sleep state. while in the sleep state, power consumption is reduced by two orders of magnitude. the part remains in the sleep state as long it is not addressed for a read/write operation. the conversion result is held indefnitely in a static shift register while the part is in the sleep state. the device will not acknowledge an external request dur - ing the conversion state. after a conversion is fnished, the device is ready to accept a read/write request. once the ltc2495 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (scl). there is no latency in the conver - sion result. the data output is 24 bits long and contains a 16-bit plus sign conversion result. data is updated on the falling edges of scl allowing the user to reliably latch data on the rising edge of scl. a new conversion is initiated by a stop condition following a valid write operation or an incomplete read operation. the conversion automatically begins at the conclusion of a complete read cycle (all 24 bits read out of the device). ease of use the ltc2495 data output has no latency, flter settling delay, or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog inputs is straightforward. each conver - sion, immediately following a newly selected input or mode, is valid and accurate to the full specifcations of the device. the ltc2495 automatically performs offset and full-scale calibration every conversion cycle independent of the input channel selected. this calibration is transparent to the user a pplications i n f or m ation figure 1. state transition table and has no effect on the operation cycle described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel and temperature drift. easy drive input current cancellation the ltc2495 combines a high precision, delta-sigma adc with an automatic, differential, input current cancellation front end. a proprietary front-end passive sampling network transparently removes the differential input current. this enables external rc networks and high impedance sen - sors to directly interface to the ltc2495 without external amplifers. the remaining common mode input current is eliminated by either balancing the differential input im - pedances or setting the common mode input equal to the common mode reference (see the automatic differential input current cancellation section). this unique architec - ture does not require on-chip buffers, thereby enabling signals to swing beyond ground and v cc . moreover, the conversion sleep 2495 f01 yes no acknowledge yes no stop or read 24 bits data output/input power-on reset default configuration: in + = ch0, in ? = ch1 50hz/60hz rejection 1x output, gain = 1 ltc2495 2495fd cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full-scale + offset + linearity + drift) is maintained even with external rc networks. power-up sequence the ltc2495 automatically enters an internal reset state when the power supply voltage, v cc , drops below a threshold of approximately 2.0v. this feature guarantees the integrity of the conversion result and input channel selection. when v cc rises above this threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 4ms. the por signal clears all internal registers. the conversion immediately following a por cycle is performed on the input channels in + = ch0 and in C = ch1 with simultaneous 50hz/60hz rejection, 1x output rate, and gain = 1. the frst conversion following a por cycle is accurate within the specifcation of the device if the power supply voltage is restored to (2.7v to 5.5v) before the end of the por interval. a new input channel, rejection mode, speed mode, temperature selection or gain can be programmed into the device during this frst data input/output cycle. reference voltage range this converter accepts a truly differential external reference voltage. the absolute/common mode voltage range for the ref + and ref C pins covers the entire operating range of the device (gnd to v cc ). for correct converter operation, v ref must be positive (ref + > ref C ). the ltc2495 differential reference input range is 0.1v to v cc . for the simplest operation, ref + can be shorted to v cc and ref C can be shorted to gnd. the converter output noise is determined by the thermal noise of the front-end circuits and, as such, its value in nanovolts is nearly constant with reference voltage. a decrease in reference voltage will not signifcantly improve the converters effective resolution. on the other hand, a decreased reference will improve the converters overall inl performance. input voltage range the analog inputs are truly differential with an absolute, common mode range for the ch0-ch15 and com input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2495 converts the bipolar differential input signal v in = in + C in C (where in + and in C are the selected input channels), from C fs = C 0.5 ? v ref /gain to + fs = 0.5 ? v ref /gain where v ref = ref + C ref C . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes (see table 1). signals applied to the input (ch0-ch15, com) may extend 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the input. the effect of series resistance on the converter accuracy can be evaluated from the curves presented in the input current/reference current sections. in addition, series resistors will introduce a temperature dependent error due to input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. muxout/adcin the outputs of the multiplexer (muxoutp/muxoutn) and the inputs to the adc (adcinp/adcinn) can be used to perform input signal conditioning on any of the selected input channels or simply shorted together for direct digitization. if an external amplifer is used, the ltc2495 automatically calibrates both the offset and drift of this circuit and the easy drive sampling scheme enables a wide variety of amplifers to be used. in order to achieve optimum performance, if an external amplifer is not used, short these pins directly together (adcinp to muxoutp and adcinn to muxoutn) and minimize their capacitance to ground. a pplications i n f or m ation ltc2495 2495fd i 2 c interface the ltc2495 communicates through an i 2 c interface. the i 2 c interface is a 2-wire, open-drain interface supporting multiple devices and multiple masters on a single bus. the connected devices can only pull the data line (sda) low and can never drive it high. sda is required to be exter - nally connected to the supply through a pull-up resistor. when the data line is not being driven, it is high. data on the i 2 c bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. the v cc power should not be removed from the device when the i 2 c bus is active to avoid loading the i 2 c bus lines through the internal esd protection diodes. each device on the i 2 c bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when perform - ing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. devices addressed by the master are considered a slave. the ltc2495 can only be addressed as a slave. once addressed, it can receive confguration bits (channel selection, rejection mode, speed mode) or transmit the last conversion result. the serial clock line, scl, is always an input to the ltc2495 and the serial data line sda is bidirectional. the device supports the standard mode and the fast mode for data transfer speeds up to 400kbits/s. figure 2 shows the defnition of the i 2 c timing. the start and stop conditions a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is consid - ered to be busy after the start condition. when the data transfer is fnished, a stop (p) condition is generated by transitioning sda from low to high while scl is high. the bus is free after a stop is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated start timing is functionally identical to the start and is used for writing and reading from the device before the initiation of a new conversion. data transferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not acknowledge (nack) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the clock line (scl) is low. figure 2. defnition of timing for fast/standard mode devices on the i 2 c bus a pplications i n f or m ation sd a scl s sr p s t hd(sda) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 2495 f02 ltc2495 2495fd data format after a start condition, the master sends a 7-bit address followed by a read/write (r/w) bit. the r/w bit is 1 for a read request and 0 for a write request. if the 7-bit address matches the hard wired ltc2495s address (one of 27 pin-selectable addresses) the device is selected. when the device is addressed during the conversion state, it will not acknowledge r/w requests and will issue a nack by leav - ing the sda line high. if the conversion is complete, the ltc2495 issues an ack by pulling the sda line low. the ltc2495 has two registers. the output register (24 bits long) contains the last conversion result. the input register (16 bits long) sets the input channel, selects the temperature sensor, rejection mode, gain and speed mode. data output format the output register contains the last conversion result. after each conversion is completed, the device automati - cally enters the sleep state where the supply current is reduced to 1a. when the ltc2495 is addressed for a read operation, it acknowledges (by pulling sda low) and acts as a transmitter. the master/receiver can read up to three bytes from the ltc2495. after a complete read operation (3 bytes), a new conversion is initiated. the device will nack subsequent read operations while a conversion is being performed. the data output stream is 24 bits long and is shifted out on the falling edges of scl (see figure 3a). the frst bit is the conversion result sign bit (sig) (see tables 1 and 2). this bit is high if v in 0 and low if v in < 0 (where v in corresponds to the selected input signal in + C in C ). the second bit is the most signifcant bit (msb) of the result. the frst two bits (sig and msb) can be used to indicate over and underrange conditions (see table 2). if both bits are high, the differential input voltage is equal to or above +fs. if both bits are set low, the input voltage is below Cfs. the function of these bits is summarized in table 2. the 16 bits following the msb bit are the conversion result in binary, twos complement format. the remaining six bits are always 0. as long as the voltage on the selected input channels (in + and in C ) remains between C0.3v and v cc + 0.3v (absolute maximum operating range) a conversion result is gener - ated for any differential input voltage v in from Cfs = C0.5 ? v ref /gain to +fs = 0.5 ? v ref /gain. for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to +fs. for differential input voltages below Cfs, the conversion result is clamped to the value Cfs C 1lsb. a pplications i n f or m ation table 1. output data format differential input voltage v in * bit 23 sig bit 22 msb bit 21 bit 20 bit 19 bit 6 lsb bits 5-0 always 0 v in * fs** 1 1 0 0 0 0 000000 fs** C 1lsb 1 0 1 1 1 1 000000 0.5 ? fs** 1 0 1 0 0 0 000000 0.5 ? fs** C 1lsb 1 0 0 1 1 1 000000 0 1/0 ? 0 0 0 0 0 000000 C1lsb 0 1 1 1 1 1 000000 C0.5 ? fs** 0 1 1 0 0 0 000000 C0.5 ? fs** C 1lsb 0 1 0 1 1 1 000000 Cfs** 0 1 0 0 0 0 000000 v in * < Cfs** 0 0 1 1 1 1 000000 *the differential input voltage v in = in + C in C . **the full-scale voltage fs = 0.5 ? v ref /gain. ? the sign bit changes state during the 0 output code when the device is operating in the 2x speed mode. ltc2495 2495fd table 2. ltc2495 status bits input range bit 23 sig bit 22 msb v in fs 1 1 0v v in < fs 1/ 0 0 Cfs v in < 0v 0 1 v in < Cfs 0 0 input data format the serial input word to the ltc2495 is 16 bits long and is written into the device input register in two 8-bit words. the frst word (sgl, odd, a2, a1, a0) is used to select the input channel. the second word of data (im, fa, fb, spd, gs2, gs1, gs0) is used to select the frequency rejection, speed mode (1x, 2x), temperature measure - ment and gain. after power-up, the device initiates an internal reset cycle which sets the input channel to ch0-ch1 (in + = ch0, in C = ch1), the frequency rejection to simultaneous 50hz/60hz, and 1x output rate (auto-calibration enabled), and gain = 1. the frst conversion automatically begins at power-up using this default confguration. once the conversion is complete, up to two words may be written into the device. the frst three bits of the frst input word consist of two preamble bits and one enable bit. valid settings for these three bits are 000, 100, and 101. other combinations should be avoided. if the frst three bits are 000 or 100, the following data is ig - nored (dont care) and the previously selected input channel and confguration remain valid for the next conversion. if the frst three bits shifted into the device are 101, then the next fve bits select the input channel for the next conversion cycle (see table 3). the frst input bit (sgl) following the 101 sequence de - termines if the input selection is differential (sgl = 0) or single ended (sgl = 1). for sgl = 0, two adjacent channels can be selected to form a differential input. for sgl = 1, figure 3a. timing diagram for reading from the ltc2495 a pplications i n f or m ation figure 3b. timing diagram for writing to the ltc2495 sleep data output ack by ltc2497 ack by master always low start by master nack by master lsb r msb sgn bit 21 7 ? ? 8 9 1 2 9 1 2 3 4 5 6 7 8 9 1 7-bit address 2495 f03a scl sda sleep data input ack by ltc2495 ack ltc2495 ack ltc2495 (optional 2nd byte) start by master sgl odd w 0 1 scl sda en a2 a1 a0 7 ? 8 9 1 2 9 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 1 7-bit address 2495 f03b im fa en2 fb spd gs2 gs1 gs0 ltc2495 2495fd table 3. channel selection mux address channel selection sgl odd/ sign a2 a1 a0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 com *0 0 0 0 0 in + in C 0 0 0 0 1 in + in C 0 0 0 1 0 in + in C 0 0 0 1 1 in + in C 0 0 1 0 0 in + in C 0 0 1 0 1 in + in C 0 0 1 1 0 in + in C 0 0 1 1 1 in + in C 0 1 0 0 0 in C in + 0 1 0 0 1 in C in + 0 1 0 1 0 in C in + 0 1 0 1 1 in C in + 0 1 1 0 0 in C in + 0 1 1 0 1 in C in + 0 1 1 1 0 in C in + 0 1 1 1 1 in C in + 1 0 0 0 0 in + in C 1 0 0 0 1 in + in C 1 0 0 1 0 in + in C 1 0 0 1 1 in + in C 1 0 1 0 0 in + in C 1 0 1 0 1 in + in C 1 0 1 1 0 in + in C 1 0 1 1 1 in + in C 1 1 0 0 0 in + in C 1 1 0 0 1 in + in C 1 1 0 1 0 in + in C 1 1 0 1 1 in + in C 1 1 1 0 0 in + in C 1 1 1 0 1 in + in C 1 1 1 1 0 in + in C 1 1 1 1 1 in + in C *default at power-up a pplications i n f or m ation ltc2495 2495fd one of 16 channels is selected as the positive input. the ne gative input is com for all single-ended operations. the remaining four bits (odd, a2, a1, a0) determine which channel(s) is/are selected and the polarity (for a differential input). once the frst word is written into the device, a second word may be input in order to select a confguration mode. the frst bit of the second word is the enable bit for the conversion confguration (en2). if this bit is set to 0, then the next conversion is performed using the previously selected converter confguration. if th e en2 bit is set to a 1, a new confguration can be loaded into the device (see table 4). the frst bit (im) is used to select the internal temperature sensor. if im = 1, the following conversion will be performed on the internal temperature sensor rather than the selected input channel. t he next two bits (fa and fb) are used to set the rejection frequency. the next bit (spd) is used to select either the 1x output rate if spd = 0 (auto-calibration is enabled and the offset is continuously calibrated and removed from the fnal conversion result) or the 2x output rate if spd = 1 (offset calibration disabled, multiplexing output rates up to 15hz with no latency). the fnal three bits (gs2, gs1, gs0) are used to set the gain. when im = 1 (temperature measurement) spd, gs2, gs1 and gs0 will be ignored and the device will operate in 1x mode. the confguration remains valid until a new input word with en = 1 (the frst three bits are 101 for the frst word) and en2 = 1 (for the second write byte) is shifted into the device. a pplications i n f or m ation table 4. converter confguration 1 0 en sgl odd a2 a1 a0 en2 im fa fb spd gs2 gs1 gs0 converter configuration 1 0 0 any input channel x x x x x x x x keep previous 1 0 1 0 x x x x x x x keep previous 1 0 1 1 0 any rejection mode 0 0 0 0 external input, gain = 1, auto-calibration 1 0 1 1 0 0 0 0 1 external input, gain = 4, auto-calibration 1 0 1 1 0 0 0 1 0 external input, gain = 8, auto-calibration 1 0 1 1 0 0 0 1 1 external input, gain = 16, auto-calibration 1 0 1 1 0 0 1 0 0 external input, gain = 32, auto-calibration 1 0 1 1 0 0 1 0 1 external input, gain = 64, auto-calibration 1 0 1 1 0 0 1 1 0 external input, gain = 128, auto-calibration 1 0 1 1 0 0 1 1 1 external input, gain = 264, auto-calibration 1 0 1 1 0 1 0 0 0 external input, gain = 1, 2x speed 1 0 1 1 0 1 0 0 1 external input, gain = 2, 2x speed 1 0 1 1 0 1 0 1 0 external input, gain = 4, 2x speed 1 0 1 1 0 1 0 1 1 external input, gain = 8, 2x speed 1 0 1 1 0 1 1 0 0 external input, gain = 16, 2x speed 1 0 1 1 0 1 1 0 1 external input, gain = 32, 2x speed 1 0 1 1 0 1 1 1 0 external input, gain = 64, 2x speed 1 0 1 1 0 1 1 1 1 external input, gain = 128, 2x speed 1 0 1 1 0 0 0 any speed any gain external input, simultaneous 50hz/60hz rejection 1 0 1 1 0 0 1 external input, 50hz rejection 1 0 1 1 0 1 0 external input, 60hz rejection 1 0 1 1 0 1 1 reserved, do not use 1 0 1 1 1 0 0 x x x x temperature input, simultaneous 50hz/60hz rejection 1 0 1 1 1 0 1 x x x x temperature input, 50hz rejection 1 0 1 1 1 1 0 x x x x temperature input, 60hz rejection 1 0 1 1 1 1 1 x x x x reserved, do not use ltc2495 0 2495fd rejection mode (fa, fb) the ltc2495 includes a high accuracy on-chip oscillator with no required external components. coupled with an integrated fourth-order digital lowpass flter, the ltc2495 rejects line frequency noise. in the default mode, the ltc2495 simultaneously rejects 50hz and 60hz by at least 87db. if more rejection is required, the ltc2495 can be confgured to reject 50hz or 60hz to better than 110db. speed mode (spd) every conversion cycle, two conversions are combined to remove the offset (default mode). this result is free from offset and drift. in applications where the offset is not critical, the auto-calibration feature can be disabled with the beneft of twice the output rate. while operating in the 2x mode (spd = 1), the linearity and full-scale errors are unchanged from the 1x mode performance. in both the 1x and 2x mode there is no latency. this enables input steps or multiplexer changes to settle in a single conversion cycle, easing system over - head and increasing the effective conversion rate. during temperature measurements, the 1x mode is always used independent of the value of spd. gain (gs2, gs1, gs0) the input referred gain of the ltc2495 is adjustable from 1 to 256 (see tables 5a and 5b). with a gain of 1, the differential input range is v ref /2 and the common mode input range is rail-to-rail. as the gain is increased, the differential input range is reduced to 0.5 ? v ref /gain but the common mode input range remains rail-to-rail. as the differential gain is increased, low level voltages are digitized with greater resolution. at a gain of 256, the ltc2495 digitizes an input signal range of 9.76mv with over 16,000 counts. temperature sensor the ltc2495 includes an integrated temperature sensor. the temperature sensor is selected by setting im = 1. during temperature readings, muxoutn/muxoutp remains connected to the selected input channel. the adc internally connects to the temperature sensor and performs a conversion. the digital output is proportional to the absolute tem - perature of the device. this feature allows the converter to perform cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors. a pplications i n f or m ation table 5a. performance vs gain in normal speed mode (v cc = 5v, v ref = 5v) gain 1 4 8 16 32 64 128 256 unit input span 2.5 0.625 0.312 0.156 78m 39m 19.5m 9.76m v lsb 38.1 9.54 4.77 2.38 1.19 0.596 0.298 0.149 v noise free resolution* 65536 65536 65536 65536 65536 65536 32768 16384 counts gain error 5 5 5 5 5 5 5 8 ppm of fs offset error 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 v table 5b. performance vs gain in 2x speed mode (v cc = 5v, v ref = 5v) gain 1 2 4 8 16 32 64 128 unit input span 2.5 1.25 0.625 0.312 0.156 78m 39m 19.5m v lsb 38.1 19.1 9.54 4.77 2.38 1.19 0.596 0.298 v noise free resolution* 65536 65536 65536 65536 65536 65536 45875 22937 counts gain error 5 5 5 5 5 5 5 5 ppm of fs offset error 200 200 200 200 200 200 200 200 v *the resolution in counts is calculated as the fs divided by lsb or the rms noise value, whichever is larger. ltc2495 2495fd the internal temperature sensor output is 28mv at 27c (300k), with a slope of 93.5v/c independent of v ref (see figures 4 and 5). slope calibration is not required if the reference voltage (v ref ) is known. a 5v reference has a slope of 2.45 lsbs 16 /c. the temperature is calculated from the output code (where dataout 16 is the decimal representation of the 16-bit result) for a 5v reference using the following formula: t da ta out in ke lv in k = 16 2 4 5 . if a different value of v ref is used, the temperature output is: t da ta out v in ke lv in k re f = 16 12 25 ? . if the value of v ref is not known, the slope is determined by measuring the temperature sensor at a known tempera - ture t n (in k) and using the following formula: sl op e da ta out t n = 16 this value of slope can be used to calculate further tem - perature readings using: t da ta out sl op e k = 16 all kelvin temperature readings can be converted to t c (c) using the fundamental equation: t c = t k C 273 initiating a new conversion when the ltc2495 fnishes a conversion, it automatically enters the sleep state. once in the sleep state, the device is ready for a read operation. after the device acknowledges a read request, the device exits the sleep state and enters the data output state. the data output state concludes and the ltc2495 starts a new conversion once a stop condition is issued by the master or all 24 bits of data are read out of the device. during the data read cycle, a stop command may be issued by the master controller in order to start a new conversion and abort the data transfer. this stop command must be issued during the ninth clock cycle of a byte read when the bus is free (the ack/nack cycle). ltc2495 address the ltc2495 has three address pins (ca0, ca1, ca2). each may be tied high, low, or left foating enabling one of 27 possible addresses (see table 6). in addition to the confgurable addresses listed in table 6, the ltc2495 also contains a global address (1110111) which may be used for synchronizing multiple ltc2495s or other ltc24xx delta-sigma i 2 c devices (see synchronizing multiple ltc2495s with a global address call section). a pplications i n f or m ation figure 4. internal ptat digital output vs temperature figure 5. absolute temperature error temperature (k) 0 dataout 16 450 600 750 900 1050 400 2495 f04 300 0 300 200 100 150 v cc = 5v v ref = 5v slope = 2.45 lsb 16 /k temperature (c) ?55 ?30 ?5 absolute error (c) 5 4 3 2 1 ?4 ?3 ?2 ?1 0 120 95 70 45 20 2495 f05 ?5 ltc2495 2495fd figure 6. conversion sequence figure 7. consecutive reading with the same input/confguration table 6. address assignment ca2 ca1 ca0 address low low low 0010100 low low high 0010110 low low float 0010101 low high low 0100110 low high high 0110100 low high float 0100111 low float low 0010111 low float high 0100101 low float float 0100100 high low low 1010110 high low high 1100100 high low float 1010111 high high low 1110100 high high high 1110110 high high float 1110101 high float low 1100101 high float high 1100111 high float float 1100110 float low low 0110101 float low high 0110111 float low float 0110110 float high low 1000111 float high high 1010101 float high float 1010100 float float low 1000100 float float high 1000110 float float float 1000101 a pplications i n f or m ation operation sequence the ltc2495 acts as a transmitter or receiver, as shown in figure 6. the device may be programmed to perform several functions. these include input channel selection, measure the internal temperature, selecting the line fre - quency rejection (50hz, 60hz, or simultaneous 50hz and 60hz), a 2x speed mode and gain. continuous read in applications where the input channel/confguration does not need to change for each cycle, the conversion can be continuously performed and read without a write cycle (see figure 7). the confguration/input channel remains unchanged from the last value written into the device. if the device has not been written to since power up, the confguration is set to the default value. at the end of a read operation, a new conversion automatically begins. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not concluded and a valid address selects the device, the ltc2495 generates a nack signal indicating the conversion cycle is in progress. continuous read/write once the conversion cycle is concluded, the ltc2495 can be written to and then read from using the repeated start (sr) command. figure 8 shows a cycle which begins with a data write, a repeated start, followed by a read and concluded with a stop command. the following conversion begins after all s ack d at a sr d at a transferrin g p sleep d at a input/outpu t conversion conversion 7-bit address r/w 2495 f05 7-bit address conversion conversion conversion sleep sleep d at a outpu t d at a outpu t 7-bit address s s r r ack ack read read p p 2495 f07 ltc2495 2495fd 24 bits are read out of the device or after a stop command . th e following conversion will be performed using the newly programmed data. in cases where the same speed (1x/2x mode), rejection frequency (50hz, 60hz, 50hz and 60hz) and gain is used but the channel is changed, a stop or repeated start may be issued after the frst byte (channel selection data) is written into the device. discarding a conversion result and initiating a new conversion with optional write at the conclusion of a conversion cycle, a write cycle can be initiated. once the write cycle is acknowledged, a stop command will start a new conversion. if a new input channel or conversion confguration is required, this data can be written into the device and a stop command will initiate the next conversion (see figure 9). figure 10. synchronize multiple ltc2495s with a global address call synchronizing multiple ltc2495s with a global address call in applications where several ltc2495s (or other i 2 c delta- sigma adcs from linear technology corporation) are used on the same i 2 c bus, all converters can be synchronized through the use of a global address call. prior to issuing the global address call, all converters must have completed a conversion cycle. the master then issues a start, followed by the global address 1110111, and a write request. all converters will be selected and acknowledge the request. the master then sends a write byte (optional) followed by the stop command. this will update the channel selection (optional) converter confguration (optional) and simultane - ously initiate a start of conversion for all delta-sigma adcs on the bus (see figure 10). in order to synchronize multiple converters without changing the channel or confguration, a stop may be issued after acknowledgement of the global write command. global read commands are not allowed and the converters will nack a global read request. a pplications i n f or m ation figure 8. write, read, start conversion figure 9. start a new conversion without reading old conversion result 7-bit address conversion conversion address sleep data output d at a inpu t 7-bit address s r w ack ack write sr p read 2495 f08 7-bit address conversion conversion sleep d at a inpu t s w ack write (optional) p 2495 f09 global address scl sda ltc2495 ltc2495 ltc2495 ? all l tc2495s in sleep conversion of all l tc2495 s data input s w ack write (optional) p 2495 f10 ltc2495 2495fd driving the input and reference the input and reference pins of the ltc2495 are connected directl y to a switched capacitor network. depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. each time a capacitor is switched between two of these pins, a small amount of charge is transferred. a simplifed equivalent circuit is shown in figure 11. when using the ltc2495s internal oscillator, the input capacitor array is switched at 123khz. the effect of the charge transfer depends on the circuitry driving the input/reference pins. if the total external rc time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs. typically, the reference inputs are driven from a low impedance source. in this case, complete settling occurs even with large external bypass capacitors. the inputs (ch0-ch15, com), on the other hand, are typically driven from larger source resistances. source resistances up to 10k may interface directly to the ltc2495 and settle completely; however, the addition of external capacitors figure 11. equivalent analog input circuit at the input terminals in order to flter unwanted noise (anti-aliasing) results in incomplete settling. the ltc2495 offers two methods of removing these errors. the frst is automatic differential input current cancellation (easy drive) and the second is the insertion of an external buffer between the muxout and adcin pins, thus isolating the input switching from the source resistance. automatic differential input current cancellation in applications where the sensor output impedance is low (up to 10k w with no external bypass capacitor or up to 500 w with 0.001f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization is possible. for many applications, the sensor output impedance combined with external input bypass capacitors produces rc time constants much greater than the 580ns required for 1ppm accuracy. for example, a 10k w bridge driving a 0.1f capacitor has a time constant an order of magnitude greater than the required maximum. the ltc2495 uses a proprietary switching algorithm that forces the average differential input current to zero a pplications i n f or m ation i i n i in v v r i r ef avg avg in cm re f c m eq + ( ) = ( ) = ? ? ? ( ) ( ) . 0 5 + + ( ) + ( ) avg re f r ef cm in cm eq in v v v r v v 1 5 0 5 2 . ? . ? ? ( ) ( ) r re f e q re f re f c m r wh er e v r ef re f v re f r ef ? : ? ( ) = ? = + ? + ? 2 ? ? ? ? ? ? ? ? ? = ? + ? + ? v i n i n w he re in an d i n a re th e s elec t in , e ed in pu t c ha nn els v in in r in cm eq ( ) ? . = ? ? ? ? ? ? ? ? = + ? 2 2 7 1 1 6 0 m i n te rna l o sci lla to r h z m ode w r 2.98 m i n te rna eq = w l l o sci lla to r 50h z/ 60h z m ode r 0.833 10 /f eq 12 eo s = ? ( ) c c ex te rna l o sci lla to r in + in ? 10k internal switch network 10k c eq 12 f 10k i in ? ref + i ref + i in + i ref ? 2495 f11 switching frequency f sw = 123khz internal oscillator f sw = 0.4 ? f eosc external oscillator ref ? 10k 100 input multiplexer external connection 100 muxoutp adcinp external connection muxoutn adcinn ltc2495 2495fd independent of external settling errors. this allows direct d igitization of high impedance sensors without the need for buffers. the switching algorithm forces the average input current on the positive input (i in + ) to be equal to the average input current on the negative input (i in C ). over the complete conversion cycle, the average differential input current (i in + C i in C ) is zero. while the differential input current is zero, the common mode input current (i in + + i in C )/2 is proportional to the difference between the common mode input voltage (v in(cm) ) and the common mode reference voltage (v ref(cm) ). in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and com - mon mode input current are zero. the accuracy of the converter is not compromised by settling errors. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between v in(cm) and v ref(cm) . for a reference common mode voltage of 2.5v and an input common mode of 1.5v, the common mode input current is approximately 0.74a (in simultaneous 50hz/60hz rejection mode). this common mode input current does not degrade the accuracy if the source impedances tied to in + and in C are matched. mismatches in source impedance lead to a fxed offset error but do not effect the linearity or full-scale reading. a 1% mismatch in a 1k source resistance leads to a 74v shift in offset voltage. in applications where the common mode input voltage varies as a function of the input signal level (single-ended type sensors), the common mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2495, leading to little degradation in accuracy. mismatches in source impedances lead to gain errors proportional to the dif - ference between the common mode input and common mode reference. a 1% mismatch in 1k source resistances lead to gain errors on the order of 15ppm. based on the stability of the internal sampling capacitors and the ac - curacy of the internal oscillator, a one-time calibration will remove this error. in addition to the input sampling current, the input esd protection diodes have a temperature dependent leakage figure 12. external buffers provide high impedance inputs and amplifer offsets are automatically cancelled a pplications i n f or m ation ? + ? + 1/2 ltc6078 1/2 ltc6078 1 2 3 5 6 7 $ 3 adc with easy drive inputs input mux muxoutp muxoutn 17 2495 f12 ltc2495 analog inputs scl sda 0.1f 1k 1k 0.1f ltc2495 2495fd current. this current, nominally 1na (10na max), results in a small offset shift. a 1k source resistance will create a 1v typical and a 10v maximum offset voltage. automatic offset calibration of external buffers/ amplifers in addition to the easy drive input current cancellation, the ltc2495 allows an external amplifer to be inserted between the multiplexer output and the adc input (see figure 12). this is useful in applications where balanced source impedances are not possible. one pair of external buffers/amplifers can be shared between all 17 analog inputs. the ltc2495 performs an internal offset calibration every conversion cycle in order to remove the offset and drift of the adc. this calibration is performed through a combination of front-end switching and digital process - ing. since the external amplifer is placed between the multiplexer and the adc, it is inside this correction loop. this results in automatic offset correction and offset drift removal of the external amplifer. the ltc6078 is an excellent amplifer for this function. it operates with supply voltages as low as 2.7v and its noise level is 18nv/ hz . the easy drive input technology of the ltc2495 enables an rc network to be added directly to the output of the ltc6078. the capacitor reduces the magnitude of the current spikes seen at the input to the adc and the resistor isolates the capacitor load from the op amp output enabling stable operation. the ltc6078 can also be biased at supply rails beyond those used by the ltc2495. this allows the external sensor to swing rail- to-rail (C0.3v to v cc + 0.3v) without the need of external level-shift circuitry. reference current similar to the analog inputs, the ltc2495 samples the differential reference pins (ref + and ref C ) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. if incomplete set - tling occurs (as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. for relatively small values of external reference capacitance (c ref < 1nf), the voltage on the sampling capacitor settles for reference impedances of many k w ( if c ref = 100pf up to 10k w will not degrade the performance (see figures 13 and 14) ) . in cases where large bypass capacitors are required on the reference inputs (c ref > 0.01f), full-scale and linear - ity errors are proportional to the value of the reference resistance. every ohm of reference resistance produces a full-scale error of approximately 0.5ppm ( while operat - ing in simultaneous 50hz/60hz mode (see figures 15 and 16) ) . if the input common mode voltage is equal to the reference common mode voltage, a linearity error of approximately 0.67ppm per 100 w of reference resistance figure 13. +fs error vs r source at v ref (small c ref ) figure 14. Cfs error vs r source at v ref (small c ref ) a pplications i n f or m ation r source ( ) 0 +fs error (ppm) 50 70 90 10k 2495 f13 30 10 40 60 80 20 0 ?10 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf r source ( ) 0 ?fs error (ppm) ?30 ?10 10 10k 2495 f14 ?50 ?70 ?40 ?20 0 ?60 ?80 ?90 10 100 1k 100k v cc = 5v v ref = 5v v in + = 1.25v v in ? = 3.75v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf ltc2495 2495fd figure 17. inl vs differential input voltage and reference source resistance for c ref > 1f figure 19. input normal mode rejection, internal oscillator and 60hz rejection mode figure 18. input normal mode rejection, internal oscillator and 50hz rejection mode results (see figure 17). in applications where the input and reference common mode voltages are different, the errors increase. a 1v difference in between common mode input and common mode reference results in a 6.7ppm inl error for every 100 w of reference resistance. in addition to the reference sampling charge, the reference esd protection diodes have a temperature dependent leak - age current. this leakage current, nominally 1na (10na max) results in a small gain error. a 100 w reference resistance will create a 0.5v full-scale error. normal mode rejection and anti-aliasing one of the advantages delta-sigma adcs offer over conventional adcs is on-chip digital fltering. combined with a large oversample ratio, the ltc2495 signifcantly simplifes anti-aliasing flter requirements. additionally, the input current cancellation feature allows external lowpass fltering without degrading the dc performance of the device. the sinc 4 digital flter provides excellent normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ) (see figures 18 and 19). the modulator sampling frequency is f s = 15,360hz while operating with its internal oscillator and f s = f eosc /20 when operating with an external oscillator of frequency f eosc . a pplications i n f or m ation figure 15. +fs error vs r source at v ref (large c ref ) figure 16. Cfs error vs r source at v ref (large c ref ) r source ( ) 0 +fs error (ppm) 300 400 500 800 2495 f15 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f r source ( ) 0 ?fs error (ppm) ?200 ?100 0 800 2495 f16 ?300 ?400 ?500 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in ? = 3.75v f o = gnd t a = 25c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f v in /v ref ?0.5 inl (ppm of v ref ) 2 6 10 0.3 2495 f17 ?2 ?6 0 4 8 ?4 ?8 ?10 ?0.3 ?0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c c ref = 10f r = 1k r = 100 r = 500 differential input signal frequency (hz) 0 f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2495 f18 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 differential input signal frequency (hz) 0 f s input normal mode rejection (db) 2495 f19 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s ltc2495 2495fd figure 21. input normal mode rejection at f s = 256 ? f n figure 20. input normal mode rejection at dc a pplications i n f or m ation figure 22. input normal mode rejection vs input frequency with input perturbation of 100% (60hz notch) figure 23. input normal mode rejection vs input frequency with input perturbation of 100% (50hz notch) input signal frequency (hz) input normal mode rejection (db) 2495 f20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n f n = f eosc/5120 input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2495 f21 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 f n = f eosc/5120 input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2495 f23 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2495 f24 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data ltc2495 2495fd figure 26. measure input normal mode rejection vs input frequency with input perturbation of 150% (50hz notch) figure 25. measure input normal mode rejection vs input frequency with input perturbation of 150% (60hz notch) a pplications i n f or m ation figure 24. input normal mode rejection vs input frequency with input perturbation of 100% (50hz/60hz notch) when using the internal oscillator, the ltc2495 is designed to reject line frequencies. as shown in figure 20, rejec - tion nulls occur at multiples of frequency f n , where f n is determined by the input control bits fa and fb (f n = 50hz or 60hz or 55hz for simultaneous rejection). multiples of the modulator sampling rate (f s = f n ? 256) only reject noise to 15db (see figure 21); if noise sources are present at these frequencies anti-aliasing will reduce their effects. the user can expect to achieve this level of performance using the internal oscillator, as shown in figures 22, 23, and 24. measured values of normal mode rejection are shown superimposed over the theoretical values in all three rejection modes. traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. the proprietary architecture used for the ltc2495 third-order modulator resolves this problem and guarantees stability with input signals 150% of full scale. in many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts if peak-to-peak noise. figures 25 and 26 show measurement results for the rejection of a 7.5v peak- to-peak noise source (150% of full scale) applied to the ltc2495. these curves show that the rejection performance is maintained even in extremely noisy environments. input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 normal mode rejection (db) 2495 f25 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2495 f26 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) input frequency (hz) 0 normal mode rejection (db) 2495 f27 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 ltc2495 0 2495fd using the 2x speed mode of the ltc2495 alters the rej ection characteristics around dc and multiples of f s . the device bypasses the offset calibration in order to increase the output rate. the resulting rejection plots are shown in figures 27 and 28. 1x type frequency rejection can be achieved using the 2x mode by performing a run - ning average of the previous two conversion results (see figure 29). output data rate when using its internal oscillator, the ltc2495 produces up to 15 samples per second (sps) with a notch frequency of 60hz. the actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignifcantly short. when operating with an external conversion clock (f o connected to an external oscillator), the ltc2495 output data rate can be increased. the duration of the conversion cycle is 41036/f eosc . if f eosc = 307.2khz, the converter behaves as if the internal oscillator is used. an increase in f eosc over the nominal 307.2khz will trans- late into a proportional increase in the maximum output data rate (up to a maximum of 100sps). the increase in output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. when using the integrated temperature sensor, the internal oscillator should be used or an external oscil - lator f eosc = 307.2khz maximum. a change in f eosc results in a proportional change in the internal notch position. this leads to reduced differential mode rejection of line frequencies. the common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the in + and in C pins will continue to reject line frequency noise. an increase in f eosc also increases the effective dynamic input and reference current. external rc networks will continue to have zero differential input current, but the time required for complete settling (580ns for f eosc = 307.2khz) is reduced, proportionally. once the external oscillator frequency is increased above 1mhz (a more than 3x increase in output rate) the effective - ness of internal auto calibration circuits begins to degrade. this results in larger offset errors, full-scale errors, and decreased resolution, as seen in figures 30 to 37. figure 27. input normal mode rejection 2x speed mode figure 28. input normal mode rejection 2x speed mode a pplications i n f or m ation input signal frequency (f n ) input normal rejection (db) 2495 f27 0 ?20 ?40 ?60 ?80 ?100 ?120 0 f n 2f n 3f n 4f n 5f n 6f n 7f n 8f n input signal frequency (f n ) input normal rejection (db) 2495 f28 0 ?20 ?40 ?60 ?80 ?100 ?120 250 248 252 254 256 258 260 262 264 ltc2495 2495fd figure 29. input normal mode rejection 2x speed mode with and without running averaging figure 30. offset error vs output data rate and temperature figure 31. +fs error vs output data rate and temperature figure 32.Cfs error vs output data rate and temperature figure 33. resolution (noise rms 1lsb) vs output data rate and temperature figure 34. resolution (inl max 1lsb) vs output data rate and temperature figure 36. resolution (noise rms 1lsb) vs output data rate and temperature figure 37. resolution (inl max 1lsb) vs output data rate and temperature figure 35. offset error vs output data rate and temperature a pplications i n f or m ation differential input signal frequency (hz) 48 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 54 58 2495 f29 50 52 56 60 62 normal mode rejection (db) no average with running average output data rate (readings/sec) ?10 offset error (ppm of v ref ) 10 30 50 0 20 40 20 40 60 80 2495 f30 100 10 0 30 50 70 90 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 50 70 2495 f31 1000 3000 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 ?3500 ?fs error (ppm of v ref ) ?3000 ?2000 ?1500 ?1000 0 10 50 70 2495 f32 ?2500 ?500 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 50 70 2495 f33 14 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock res = log 2 (v ref /noise rms ) t a = 25c, 85c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 50 70 14 40 90 100 20 30 60 80 t a = 85c t a = 25c v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock res = log 2 (v ref /inl max ) 2495 f34 output data rate (readings/sec) 0 ?10 offset error (ppm of v ref ) ?5 5 10 20 10 50 70 2495 f35 0 15 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25 o c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 50 70 2495 f36 14 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25 o c res = log 2 (v ref /noise rms ) v cc = 5v, v ref = 2.5v, 5v output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 50 70 14 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v ref ? = gnd f o = ext clock t a = 25c res = log 2 (v ref /inl max ) 2495 f37 ltc2495 2495fd p ackage description uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) 5.00 p 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 p 0.10 0.75 p 0.05 r = 0.125 typ r = 0.10 typ 0.25 p 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 p 0.10 0.70 p 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 p 0.05 5.50 p 0.05 5.15 0.05 6.10 p 0.05 7.50 p 0.05 0.25 p 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer ltc2495 2495fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h istory rev date description page number c 11/09 update tables 1 and 2 16 d 07/10 revised typical application drawing 1 added f o pin to parameter of v iha in i 2 c inputs and outputs section 4 added information to i 2 c interface section 15 (revision history begins at rev c) ltc2495 2495fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0710 rev d ? printed in usa part number description comments lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift lt1790 micropower sot-23 low dropout reference family 0.05% max initial accuracy, 10ppm/c max drift ltc2400 24-bit, no latency ds adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410 24-bit, no latency ds adc with differential inputs 0.8v rms noise, 2ppm inl ltc2411/ ltc2411-1 24-bit, no latency ds adcs with differential inputs in msop 1.45v rms noise, 4ppm inl, simultaneous 50hz/60hz rejection (ltc2411-1) ltc2413 24-bit, no latency ds adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2440 24-bit, high speed, low noise ds adc 3.5khz output rate, 200nv noise, 24.6 enobs ltc2442 24-bit, high speed, 2-/4-channel ds adc with integrated amplifer 8khz output rate, 200nv noise, simultaneous 50hz/60hz rejection ltc2449 24-bit, high speed, 8-/16-channel ds adc 8khz output rate, 200nv noise, simultaneous 50hz/60hz rejection ltc2480/ltc2482/ ltc2484 16-bit/24-bit ds adcs with easy drive inputs, 600nv noise, programmable gain, and temperature sensor pin compatible with 16-bit and 24-bit versions ltc2481/ltc2483/ ltc2485 16-bit/24-bit ds adcs with easy drive inputs, 600nv noise, i 2 c interface, programmable gain, and temperature sensor pin compatible with 16-bit and 24-bit versions ltc2496 16-bit 8-/16-channel ds adc with easy drive inputs and spi interface pin compatible with ltc2498/ltc2449 ltc2497 16-bit 8-/16-channel ds adc with easy drive inputs and i 2 c interface pin compatible with ltc2495/ltc2499 ltc2498 24-bit 8-/16-channel ds adc with easy drive inputs and spi interface, temperature sensor pin compatible with ltc2496/ltc2449 ltc2499 24-bit 8-/16-channel ds adc with easy drive inputs and i 2 c interface pin compatible with ltc2495/ltc2497 r elate d p arts t ypical a pplication external buffers provide high impedance inputs and amplifer offsets are automatically cancelled ? + ? + 1/2 ltc6078 1/2 ltc6078 1 2 3 5 6 7 $ 3 adc with easy drive inputs input mux muxoutp muxoutn 17 2495 ta03 ltc2495 analog inputs scl sda 1k 1k 0.1f 0.1f |
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